1. Field of the Invention
This invention relates to semiconductor technologies, and more particularly, to an substrate-triggering electrostatic discharge (ESD) protection circuit for use on a deep-submicron integrated circuit for ESD protection of the internal circuit thereof against ESD stress.
2. Description of Related Art
In the fabrication of integrated circuits, electrostatic discharge (ESD) is a major problem that can cause damage to the internal circuit of the integrated circuits. One solution to this problem is to incorporate an ESD protection circuit through an on-chip method on the input/output (I/O) pads of CMOS (complementary metal-oxide semiconductor) devices. However, as the semiconductor fabrication technologies have advanced to the deep-submicron level of integration, the conventional ESD protection circuit is no longer suitable for use to provide adequate ESD robustness. This problem will be illustratively depicted in the following with reference to FIGS. 1-3.
FIG. 1 is a schematic circuit diagram of a conventional ESD protection circuit connected to the input stage 10 of the internal circuit of an integrated circuit. As shown, an ESD protection circuit, which includes a field oxide device (FOD) F1, a resistor R1, and a gate-grounded NMOS transistor N1, is incorporated between an input pad IP and the input stage 10 (which is a CMOS device including a pair of serially connected PMOS transistor and NMOS transistor). The FOD F1 has a drain connected to the input pad IP and a source connected to the ground V.sub.SS. The resistor R1 is connected between the input pad IP and the input stage 10. The NMOS transistor N1 has a drain connected to the node between the resistor R1 and the input stage 10, a source connected to the ground V.sub.SS, and a gate tied to the source to be connected together to the ground V.sub.SS. When an over-stress voltage due to ESD is applied to the input pad IP, it will pass through the resistor R1 to the gate oxide of the paired PMOS transistor and NMOS transistor in the input stage 10. In order to suppress the over-stress voltage across the gate oxide, the gate-grounded NMOS transistor N1 is specifically designed to operate in its breakdown mode so that the ESD current can be bypassed to the ground V.sub.SS. However, when the integrated circuit is fabricated by deep-submicron technologies, the gate oxide will be formed with a very thin thickness for high-speed and low-voltage operation. This thin thickness will cause the breakdown voltage of the gate oxide in the input stage 10 to be significantly lowered. In this case, in order to allow the ESD protection circuit to be nonetheless effective, it is required that the breakdown voltage of the gate-grounded NMOS transistor N1 should be lower than the breakdown voltage of the gate oxide in the input stage 10. To achieve this, however, the channel length of the gate-grounded NMOS transistor N1 should be made as short as possible so as to provide the desired low breakdown voltage. However, a short channel length will then undesirably make the gate-grounded NMOS transistor N1 less withstandable to a high ESD stress. The provision of the resistor R1 is a solution to this problem, in that it can reduce the ESD current flowing through the gate-grounded NMOS transistor N1. The greater the resistance of the resistor R1, the better can the resistor R1 suppress the ESD current flowing through the gate-grounded NMOS transistor N1. However, a large resistance for the resistor R1 will then undesirably cause a considerable time delay to the signal being transferred from the input pad IP to the input stage 10 of the associated integrated circuit, causing a degrade in the performance of this integrated circuit. From the foregoing description, it can be learned that the use of the ESD protection circuit of FIG. 1 in an IC will encounter a number of tradeoff problems in the design of this ESD protection circuit.
In the circuit of FIG. 1, the FOD F1 is used to pick the ESD current in the input pad IP. This FOD F1 is formed without an LDD (lightly-doped drain) structure, so that it has a higher strength to withstand ESD current than the gate-grounded NMOS transistor N1. In practice, if the FOD F1 is fabricated by the 0.5 .mu.m CMOS technology, it would be twice greater in ESD robustness than the gate-grounded NMOS transistor N1 that has the same layout area. If the FOD F1 is formed with a long channel length, it can have a higher breakdown voltage than the gate-grounded NMOS transistor N1. The breakdown voltage of the FOD F1 can therefore be closely equal to or greater than the breakdown voltage of the gate oxide in the input stage 10. Therefore, the combination of the FOD F1 with the gate-grounded NMOS transistor N1 can provide an ESD protection capability for the input state 10 of the integrated circuit.
From recent researches, it has been found that the bias voltage applied to the substrate of the integrated circuit can be used to raise the ESD robustness. FIG. 2 is a graph showing the various I.sub.DS (drain-to-source current) versus V.sub.DS (drain-to-source voltage) characteristics of the FOD F1 and gate-grounded NMOS transistor N1 in the circuit of FIG. 1 when operated in breakdown mode for various substrate bias voltages. As shown, the plot indicated by the reference numeral 20 is the I.sub.DS -V.sub.DS characteristic of the gate-grounded NMOS transistor N1 when its substrate is biased at 0 V (volt), which has a second breakdown point as indicated by the reference numeral 21; the plot indicated by the reference numeral 22 is the I.sub.DS -V.sub.DS characteristic of the FOD F1 when its substrate is biased at 0 V (volt), which has a second breakdown point as indicated by the reference numeral 23; and the plot indicated by the reference numeral 24 is the I.sub.DS -V.sub.DS characteristic of the FOD F1 when its substrate is applied with a bias voltage of 0.8 V (volt), which has a second breakdown point as indicated by the reference numeral 25. It can be clearly learned from the characteristic plots of FIG. 2 that the position of the second breakdown points of the FOD F1 and gate-grounded NMOS transistor N1 can be affected by the applied substrate bias.
The ESD robustness of the FOD can be appraised by obtaining the relationship between the second-breakdown current I.sub.t2 and the substrate bias voltage V.sub.SB. FIG. 3 is a graph in which the solid circular dots represent the I.sub.t2 -V.sub.SB characteristic of the FOD F1 in FIG. 1 when it is fabricated by a 0.5 .mu.m CMOS technology, and the hollowed square box represents the I.sub.t2 -V.sub.SB characteristic of the gate-grounded NMOS transistor N1 in FIG. 1. The magnitude of I.sub.t2 in each unit width of the channel in the FOD F1 can be raised through an adjustment in the forward bias voltage to the substrate. From FIGS. 2 and 3, it can be learned that the magnitude of I.sub.t2 in the NMOS transistor N1 with a 0-V substrate bias is about 4.8 mA/.mu.m. For the FOD F1, when a 0 V bias voltage is applied to the substrate thereof, the magnitude of I.sub.t2 therein is about 9.0 mA/.mu.m; and when a 0.8-V bias voltage is applied, the magnitude of I.sub.t2 therein will be raised to about 18.2 mA/.mu.m, which is four times larger than that of the gate-grounded NMOS transistor N1 with a 0-V substrate bias, and two times larger than that of the FOD when applied with a 0.8-V substrate bias.
Fundamentally, the ESD robustness of an ESD protection circuit is substantially proportional to the magnitude of the second-breakdown current I.sub.t2. Roughly speaking, the ESD robustness of the ESD protection circuit in human body mode (HBM) is about equal to the multiplication of the magnitude of the second-breakdown current with the value of the standard discharge resistance in HBM, i.e., 1,500 .OMEGA.. Therefore, if the substrate of the FOD is applied with a suitable bias voltage, it can provide a relatively large ESD robustness with just a small layout area on the integrated circuit,